SystemVerilog: Package imports be visible in all compilation units?

Experiment with Modelsim6.4a shows that package import is visible to all compilation units:

=============================================
//File: p.sv
package p;
int a = 1;
endpackage
=============================================
//File: a.sv
int b = 2; // external variable

import p::*;

module a;
initial begin
$unit::a = 8;
$display("a:: a = %d (expect 8)", $unit::a);
$display("a:: b = %d (expect 2)", b);
end
endmodule
==============================================
//File: b.sv
int b = 3; // external variable

import p::*;
module b;
initial begin
#1; // avoid race condition
$display("b:: a = %d (expect 8)", $unit::a);
$display("b:: b = %d (expect 3)", b);
end
endmodule
==============================================
//File: top.sv
module top;
a a();
b b();
endmodule
==============================================
// Modelsim commands:
% vlog p.sv a.sv b.sv top.sv
% vsim -c -do "run -all; quit" top
==============================================
// result:
# run -all
# a:: a = 8 (expect 8)
# a:: b = 2 (expect 2)
# b:: a = 8 (expect 8)
# b:: b = 3 (expect 3)